Germanium has been considered as an appropriate material for use in CMOS and NMOS devices. With the trend towards smaller devices, contact area on the devices has become smaller, with a substantial increase in contact resistance. The increase in contact resistance has been countered with high source/drain doping.
The minimum contact resistivity on n-type Germanium has been achieved through antimony (Sb) ion implantation combined with laser annealing, according to Miyoshi et al., VLSI 2014, P180. However, the ion implantation process can be challenging for FinFET and nanowire devices.
As a result, a method for improving the source/drain performance is desired.